Oktay Baris: Computer based control systems have pervasive influence in every aspects of our daily life, such as robot control systems, automotive systems, factory automation systems, and avionics systems.
These systems are used for safety-critical applications where a failure to respond in time may lead to catastrophic consequences. Therefore, designing time-predictable system architectures is the basis of reliable and safe real-time control systems.
The time predictability of a real-time system is evaluated at design-time with the static program analysis. In this approach, the worst-case response time of a real-time system can be derived for a particular hardware architecture without actually deploying the system. Thus, this method strongly requires time predictable and analyzable hardware architectures. On the other hand, the trend in processor design is to increase performance by including more and more processing cores in a single chip. This increases system complexity and introduces a challenge for system designers to create time predictable and analyzable architectures.
Multicore processor platforms integrate a number of processing units communicating over some form of on-chip interconnection network. The main challenge of multicore time-predictable computers is how to design on-chip communication mechanisms and protocols between different cores while maintaining time predictability and scalability. The most straightforward approach to address this challenge is to provide a temporal isolation to the communication traffic flow and the bandwidth via Time-division Multiplexing (TDM) method.
The TDM-based Network-on-chip (NoC) is the basis for time predictable communication. However, in most systems the operating system and the tasks are not aware of the NoC schedule. Therefore, we propose to expose the TDM schedule to the tasks and the operating system by developing novel time-triggered operating system components where communication and execution are synchronized with the global TDM time base.
PhD project title: Real-Time Multicore Systems
Effective start/end date 15/08/2017 → 14/08/2020
DTU supervisors: Martin Schoeberl and Jens Sparsø from the section for Embedded Systems.