Luca Pezzarossa: Hard real-time embedded systems are a class of computer systems whose temporal behavior has to be completely predictable. In recent years, we have observed an increase in the usage of field programmable gate arrays (FPGAs) to implement multi-core systems-on-chip, especially for professional and high-end hard real-time applications.
Dynamical partial reconfiguration is an emerging concept in the FPGAs industry that allows the reconfiguration of selected areas of an FPGA after its initial configuration, without affecting the functionality of the FPGA section not involved in the reconfiguration.
The PhD project explores the usage of dynamical partial reconfiguration in the context of hard real-time embedded multi-core systems-on-chip. The project is tightly linked with DTU Compute T-CREST and RTEMP projects. The project is particularly challenging due to the time predictability specification, but it also offers a variety of benefits, such as very high level of flexibility, smaller size, lower cost and reduced power consumption.
Effective start/end date 15/11/2014 → 15/08/2018
Published as PhD report: Reconfiguration of Computation and Communication Resources in Multi-Core Real-Time Embedded Systems
Supervisors: Jens Sparsø, Martin Schoeberl
Section for Embedded Systems Engineering