Hasan Baig: Genetic logic circuits are an application of synthetic biology, where parts of the DNA of a living cell are re-engineered to perform a dedicated Boolean function triggered by appropriate concentration levels of certain proteins or molecules.
These logic circuits work similar to electronic logic circuits, but are much more stochastic and hence much harder to characterize. The experimentation on these genetic circuits are usually performed in-vitro in the wet-lab, where biologists are either provided with the ready-made biological models available in the test tubes or are given a specification/recipe from which to prepare it in the lab. The objective is to analyze the model and verify its functional behavior. This analysis is performed, for example, by increasing the molar concentration of input species at any instant of time and observing the effects. It is clearly a very time consuming process, and due to mishandling of the apparatus or due to any other kind of errors, experimentation needs to be repeated.
Simulation and behavioural analysis of genetic circuits is a standard approach of functional verification prior to their physical implementation. Many software tools have been developed to perform in-silico analysis for this purpose but none of them allow users to interact with the model during runtime. The runtime interactive simulation gives the user a feeling of being in the lab performing real world experimentations.
The aim of this PhD project is to introduce a software tool, which provides a virtual laboratory environment to interactively simulate and analyse the behavior of genetic logic circuit models represented in the Systems Biology Mark-up Language (SBML). The software tool is also aimed to help users to perform the logic and timing analysis of genetic logic circuits.
15/08/2014 → 15/11/2017
Published as PhD report: Methods and Tools for the Analysis, Verification and Synthesis of Genetic Logic Circuits
The current progress of this project can be seen here.
The project demonstration videos can be seen here.
Supervisor: Jan Madsen
Section for Embedded Systems Engineering