PhD defence by Luca Pezzarossa, Thursday 7 June at 13:00, DTU Lyngby, Building 101, Room S16.
Abstract:
Hard real-time embedded systems are a class of computer systems whose temporal behavior has to be completely predictable. In recent years, we have observed an increase in the usage of field programmable gate arrays (FPGAs) to implement multi-core systems-on-chip, especially for professional and high-end hard real-time applications.
Dynamical partial reconfiguration is an emerging concept in the FPGAs industry that allows the reconfiguration of selected areas of an FPGA after its initial configuration, without affecting the functionality of the FPGA section not involved in the reconfiguration.
The PhD project explores the usage of dynamical partial reconfiguration in the context of hard real-time embedded multi-core systems-on-chip. The project is tightly linked with DTU Compute T-CREST and RTEMP projects. The project is particularly challenging due to the time predictability specification, but it also offers a variety of benefits, such as very high level of flexibility, smaller size, lower cost and reduced power consumption.
Read more about this thesis in DTU Orbit.
Supervisor: Professor Jens Sparsø, DTU Compute
Co-supervisor:
Associate Professor Martin Schoeberl, DTU Compute
Examiners:
Professor Jan Madsen, DTU Compute
Professor Diana Göhringer, Technical University Dresden
Professor Kees Goossens, Eindhoven University of Technology
Chairman:
Associate Professor Alberto Nannarelli
Everyone is welcome.